The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 27, 2022

Filed:

Jun. 24, 2020
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Hong Bok We, San Diego, CA (US);

Marcus Hsu, San Diego, CA (US);

Aniket Patil, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/18 (2006.01); H01L 23/538 (2006.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/18 (2013.01); H01L 23/5385 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 24/81 (2013.01); H01L 24/83 (2013.01); H01L 24/92 (2013.01); H01L 25/50 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/73253 (2013.01); H01L 2224/8182 (2013.01); H01L 2224/81203 (2013.01); H01L 2224/83005 (2013.01); H01L 2224/83203 (2013.01); H01L 2224/83896 (2013.01); H01L 2224/92242 (2013.01); H01L 2924/20105 (2013.01);
Abstract

Integrated circuit (IC) packages employing split, double-sided IC metallization structures to facilitate a semiconductor die module employing stacked dice, and related fabrication methods are disclosed. Multiple IC dice in the IC package are stacked and bonded together in a back-to-back, top and bottom IC die configuration in an IC die module, which can minimize the height of the IC package. The metallization structure is split between separate top and bottom metallization structures adjacent to respective top and bottom surfaces of the IC die module to facilitate die-to-die and external electrical connections to the dice. The top and bottom metallization structures can be double-sided by exposing substrate interconnects on respective inner and outer surfaces for respective die and external electrical interconnections. In other aspects, a compression bond is included between the IC dice mounted together in a back-to-back configuration to further minimize the overall height of the IC package.


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