The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 27, 2022

Filed:

Jan. 18, 2022
Applicant:

Changxin Memory Technologies, Inc., Hefei, CN;

Inventor:

Mingxing Zuo, Hefei, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 25/065 (2006.01);
U.S. Cl.
CPC ...
H01L 24/32 (2013.01); H01L 24/27 (2013.01); H01L 24/29 (2013.01); H01L 24/83 (2013.01); H01L 24/33 (2013.01); H01L 24/48 (2013.01); H01L 25/0657 (2013.01); H01L 2224/27011 (2013.01); H01L 2224/27622 (2013.01); H01L 2224/29011 (2013.01); H01L 2224/29013 (2013.01); H01L 2224/29691 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/33181 (2013.01); H01L 2224/48225 (2013.01); H01L 2924/3512 (2013.01);
Abstract

The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a substrate, a die and a first adhesive layer; a surface of the substrate is provided with an insulation layer; the die is arranged on a surface of the insulation layer via the first adhesive layer; the insulation layer is provided with at least one slot; a position of the at least one slot corresponds to at least a part of an edge of the first adhesive layer; a second adhesive layer is arranged in the at least one slot; at least a part of a surface of the second adhesive layer is connected with the first adhesive layer; and an elasticity modulus of the second adhesive layer is smaller than an elasticity modulus of the first adhesive layer.


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