The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 27, 2022

Filed:

May. 01, 2017
Applicant:

Sumco Corporation, Tokyo, JP;

Inventors:

Daisuke Hashimoto, Tokyo, JP;

Satoshi Matagawa, Tokyo, JP;

Tomohiro Hashii, Tokyo, JP;

Assignee:

SUMCO CORPORATION, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
B24B 37/08 (2012.01); B24B 37/28 (2012.01); H01L 21/02 (2006.01); H01L 21/304 (2006.01); B24B 37/04 (2012.01); H01L 29/16 (2006.01); H01L 29/34 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02013 (2013.01); B24B 37/042 (2013.01); B24B 37/08 (2013.01); B24B 37/28 (2013.01); H01L 21/304 (2013.01); H01L 29/16 (2013.01); H01L 29/34 (2013.01);
Abstract

Provided is a method of lapping a semiconductor wafer, which can suppress the formation of a ring-shaped pattern in a nanotopography map. The method of lapping a semiconductor wafer includes: a stopping step of stopping lapping of a semiconductor wafer; a reversing step of reversing surfaces of the semiconductor wafer facing a upper plate and a lower plate after the stopping step; and a resuming step of resuming lapping of the semiconductor wafer after the reversing step while maintaining the reversal of the surfaces facing the plates.


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