The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 27, 2022

Filed:

Sep. 14, 2020
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventor:

Yutaka Uemura, Hachioji, JP;

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 8/00 (2006.01); G11C 7/22 (2006.01); G11C 7/10 (2006.01); H03K 23/52 (2006.01); G11C 29/10 (2006.01); H03K 23/00 (2006.01);
U.S. Cl.
CPC ...
G11C 7/222 (2013.01); G11C 7/106 (2013.01); G11C 7/1036 (2013.01); G11C 7/1045 (2013.01); G11C 7/1087 (2013.01); G11C 29/10 (2013.01); H03K 23/002 (2013.01); H03K 23/52 (2013.01);
Abstract

Disclosed herein is an apparatus that includes a first shift register circuit including a plurality of first latch circuits coupled in series, and a second shift register circuit including a plurality of second latch circuits coupled in series. The first and second shift register circuits are cyclically coupled. Each of the first latch circuits is configured to perform the latch operation in synchronization with a rise edge of a first clock signal. Each of the second latch circuits is configured to perform the latch operation in synchronization with a fall edge of a first clock signal when a first selection signal is in a first state. One or more first latch circuits and one or more second latch circuits are configured to be bypassed when a second selection signal indicates a predetermined value.


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