The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 27, 2022
Filed:
Nov. 11, 2019
Stmicroelectronics International N.v., Schiphol, NL;
Stmicroelectronics (Crolles 2) Sas, Crolles, FR;
Stmicroelectronics (Grenoble 2) Sas, Grenoble, FR;
Manoj Kumar, Greater Noida, IN;
Lionel Courau, Le Champ Pres Froges, FR;
Geeta, Gurgaon, IN;
Olivier Le-Briz, Saint-Gervais, FR;
STMicroelectronics International N.V., Schiphol, NL;
STMicroelectronics (Crolles 2) SAS, Crolles, FR;
STMicroelectronics (Grenoble 2) SAS, Grenoble, FR;
Abstract
An integrated circuit die has a peripheral edge and a seal ring extending along the peripheral edge and surrounding a functional integrated circuit area. A test logic circuit located within the functional integrated circuit area generates a serial input data signal for application to a first end of a sensing conductive wire line extending around the seal ring between the seal ring and the peripheral edge of the integrated circuit die. Propagation of the serial input data signal along the sensing conductive wire line produces a serial output data signal at a second end of the sensing conductive wire line. The test logic circuit compares data patterns of the serial input data signal and serial output data signal to detect damage at the peripheral edge of the integrated circuit die.