The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 20, 2022

Filed:

Sep. 30, 2020
Applicant:

Applied Materials, Inc., Santa Clara, CA (US);

Inventors:

Steven C. H. Hung, Sunnyvale, CA (US);

Benjamin Colombeau, San Jose, CA (US);

Andy Lo, Saratoga, CA (US);

Byeong Chan Lee, Pleasanton, CA (US);

Johanes F. Swenberg, Los Gatos, CA (US);

Theresa Kramer Guarini, San Jose, CA (US);

Malcolm J. Bevan, Santa Clara, CA (US);

Assignee:

Applied Materials, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 29/423 (2006.01); C30B 29/06 (2006.01); C30B 29/52 (2006.01); C23C 8/02 (2006.01); C23C 8/16 (2006.01); C23C 8/80 (2006.01); C23C 16/56 (2006.01); C23C 16/455 (2006.01);
U.S. Cl.
CPC ...
H01L 29/6681 (2013.01); C23C 8/02 (2013.01); C23C 8/16 (2013.01); C23C 8/80 (2013.01); C23C 16/45536 (2013.01); C23C 16/56 (2013.01); C30B 29/06 (2013.01); C30B 29/52 (2013.01); H01L 21/022 (2013.01); H01L 21/0228 (2013.01); H01L 21/02238 (2013.01); H01L 21/02255 (2013.01); H01L 29/42392 (2013.01); H01L 29/6653 (2013.01);
Abstract

Described is a method of manufacturing a gate-all-around electronic device. The method includes forming a thermal oxide layer though an enhanced in situ steam generation process in combination with atomic layer deposition of a low-κ layer. The thin thermal oxide layer passivates the interface between the silicon layer and the dielectric layer of the GAA. A passivation process after the deposition of the low-κ layer reduces the bulk trap and enhances the breakdown performance of the GAA transistor.


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