The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 20, 2022

Filed:

May. 07, 2019
Applicant:

Globalfoundries U.s. Inc., Santa Clara, CA (US);

Inventors:

Stefan Block, Munich, DE;

Herbert Johannes Preuthen, Dorfen, DE;

Ulrich Hensel, Radeberg, DE;

Assignee:

GLOBALFOUNDRIES U.S. INC., Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 27/02 (2006.01); H01L 27/12 (2006.01); H01L 29/861 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66121 (2013.01); H01L 27/0255 (2013.01); H01L 27/1207 (2013.01); H01L 29/861 (2013.01);
Abstract

Aspects of the disclosure provide a semiconductor device and method of manufacturing. Embodiments of the disclosure enable placing of protective structures without modifying spacing rules. The device includes a first device region defined above a substrate, the first device region being isolated from the substrate by a buried insulating layer. The first device region includes a first power rail, a first signal line traversing at least a first portion of the first device region, and a first plurality of edge cells positioned in the substrate adjacent the first device region. A first edge cell includes a substrate contact connecting the first power rail to the substrate and a first signal line antenna diode connecting the first signal line to the substrate.


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