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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11450732 B1

PDFFull Text
Date of Patent:
Sep. 20, 2022

Filed:

Mar. 05, 2020

Structure for capacitor protection, package structure, and method of forming package structure

Applicant:

Suzhou Tf-amd Semiconductor Co. Ltd., Suzhou, CN;

Inventors:

Zhe Liu, Suzhou, CN;

Borrong Huang, Suzhou, CN;

Hongjie Wang, Suzhou, CN;

Diong Hing Ding, Suzhou, CN;

Assignee:

SUZHOU TF-AMD SEMICONDUCTOR CO. LTD., Suzhou, CN;

Attorney:
Primary Examiner:

Duy T Nguyen

Int. Cl.
CPC ...
H01L 21/48 (2006.01); H01L 21/50 (2006.01); H01L 23/367 (2006.01); H01L 23/373 (2006.01); H01L 23/64 (2006.01); H01L 21/60 (2006.01); H01L 49/02 (2006.01);
U.S. Cl.
CPC ...
H01L 28/40 (2013.01); H01L 21/4871 (2013.01); H01L 21/50 (2013.01); H01L 23/3672 (2013.01); H01L 23/3737 (2013.01); H01L 23/642 (2013.01); H01L 2021/60135 (2013.01);
Abstract

A package structure includes: a substrate; a chip arranged on a part of a surface of the substrate; a metal thermal conducting layer arranged on a top surface of the chip; a capacitive structure arranged on another part of the surface of the substrate and arranged to be independent from the chip; and a cover including a first cover layer and a second cover layer connected to the first cover layer. A first opening is defined to extend through the first and the second cover layers. The second cover layer is arranged on a bottom of the first cover layer and perpendicular to the first cover layer. The first cover layer is arranged on the capacitive structure. The chip is received in the first opening. The second cover layer is arranged between the capacitive structure and the chip, and is fixed to the substrate.

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Liu, Zhe. (2022). Structure for capacitor protection, package structure, and method of forming package structure (U.S. Patent No. 11450732). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11450732

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