The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 20, 2022
Filed:
Sep. 12, 2019
Applicant:
United Microelectronics Corp., Hsin-Chu, TW;
Inventors:
Jin-Yan Chiou, Tainan, TW;
Wei-Chuan Tsai, Changhua County, TW;
Yen-Tsai Yi, Tainan, TW;
Li-Han Chen, Tainan, TW;
Hsiang-Wen Ke, Kaohsiung, TW;
Assignee:
UNITED MICROELECTRONICS CORP., Hsin-Chu, TW;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 29/66 (2006.01); H01L 21/285 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76856 (2013.01); H01L 21/28518 (2013.01); H01L 21/76805 (2013.01); H01L 21/76843 (2013.01); H01L 21/76889 (2013.01); H01L 21/76895 (2013.01); H01L 29/66795 (2013.01);
Abstract
A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a source/drain region adjacent to two sides of the gate structure; forming an interlayer dielectric (ILD) layer on the gate structure; forming a contact hole in the ILD layer to expose the source/drain region; forming a barrier layer in the contact hole; performing an anneal process; and performing a plasma treatment process to inject nitrogen into the contact hole.