The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 20, 2022

Filed:

Mar. 24, 2020
Applicant:

Rambus Inc., Sunnyvale, CA (US);

Inventors:

Frederick A. Ware, Los Altos Hills, CA (US);

John Eric Linstadt, Palo Alto, CA (US);

Carl W. Werner, Los Gatos, CA (US);

Assignee:

Rambus Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/04 (2006.01); G06F 1/12 (2006.01); G11C 7/22 (2006.01); G11C 29/02 (2006.01); G11C 29/50 (2006.01); H03K 5/15 (2006.01); H01L 39/22 (2006.01);
U.S. Cl.
CPC ...
G11C 7/04 (2013.01); G06F 1/12 (2013.01); G11C 7/222 (2013.01); G11C 29/022 (2013.01); G11C 29/023 (2013.01); G11C 29/50012 (2013.01); G11C 2207/2254 (2013.01); H01L 39/223 (2013.01); H03K 5/15 (2013.01);
Abstract

In a chip-to-chip signaling system includes at least one signaling link coupled between first and second ICs, the first IC has an interface coupled to the signaling link and timed by a first interface timing signal. The second IC has an interface coupled to the signaling link and timed by a second interface timing signal that is mesochronous with respect to the first interface timing signal. The second IC further has phase adjustment circuitry that adjusts a phase of the second interface timing signal using a digital counter implemented with Josephson-junction circuit elements.


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