The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 20, 2022

Filed:

Dec. 16, 2020
Applicant:

Nxp Usa, Inc., Austin, TX (US);

Inventors:

Wenzhong Zhang, Tianjin, CN;

Ajay Kumar Sharma, Dwarka, IN;

Rishi Bhooshan, Greater Noida, IN;

Assignee:

NXP USA, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/394 (2020.01); H03K 17/693 (2006.01); H01L 23/495 (2006.01); G06F 30/392 (2020.01); G06F 30/34 (2020.01);
U.S. Cl.
CPC ...
G06F 30/394 (2020.01); G06F 30/34 (2020.01); G06F 30/392 (2020.01); H01L 23/4951 (2013.01); H03K 17/693 (2013.01);
Abstract

Area and routing overhead issues of traditional anamux incorporation in a semiconductor device are overcome by placing a functional anamux block on top of an I/O pad. In some embodiments, multiple anamux blocks can be stacked either vertically or placed on neighboring I/O pads for horizontal stacking. Embodiments provide the anamux blocks as the same width as the I/O pads and the width is optimized to minimize padring height. In some embodiments, a power/ground I/O (PGE) bond pad architecture is enabled by the incorporation of both I/O pad and anamux blocks in the same region, providing two bonding regions, which can further reduce chip area. Some embodiments also permit routing of signals through the anamux block to neighboring blocks and the I/O channels.


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