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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11449656 B1

PDFFull Text
Date of Patent:
Sep. 20, 2022

Filed:

Sep. 23, 2020

Method of designing semiconductor device

Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Shao-Huan Wang, Hsinchu, TW;

Sheng-Hsiung Chen, Zhubei, TW;

Wen-Hao Chen, Hsin-Chu, TW;

Chun-Chen Chen, Hsinchu, TW;

Hung-Chih Ou, Hsinchu, TW;

Assignee:

TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu, TW;

Attorney:

Hauptman Ham, LLP

Primary Examiner:

Phallaka Kik

Int. Cl.
CPC ...
G06F 30/394 (2020.01); G06F 30/20 (2020.01); G06F 30/327 (2020.01); G06F 30/392 (2020.01); G06F 30/3312 (2020.01); G06F 30/33 (2020.01); G06F 30/337 (2020.01); G06F 30/373 (2020.01); G06F 30/398 (2020.01); H01L 23/52 (2006.01); H01L 23/522 (2006.01); G06F 111/04 (2020.01); G06F 119/12 (2020.01);
U.S. Cl.
CPC ...
G06F 30/394 (2020.01); G06F 30/20 (2020.01); G06F 30/327 (2020.01); G06F 30/3312 (2020.01); G06F 30/392 (2020.01); G06F 30/33 (2020.01); G06F 30/337 (2020.01); G06F 30/373 (2020.01); G06F 30/398 (2020.01); G06F 2111/04 (2020.01); G06F 2119/12 (2020.01); H01L 23/5226 (2013.01);
Abstract

A method including selecting a plurality of layout patterns, wherein each of the layout patterns comprises a corresponding via pillar structure that satisfies an electromigration (EM) rule, wherein each of the via pillar structures comprises metal layers and at least one via coupled to the metal layers. The method further includes selecting a layout pattern from the plurality of layout patterns having a smallest physical size. The method further includes performing a placement and routing process by using the selected layout pattern.

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