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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11444098 B1

PDFFull Text
Date of Patent:
Sep. 13, 2022

Filed:

Apr. 16, 2020

Vertical non-volatile memory devices and methods of programming the same

Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Younghwan Son, Hwaseong-si, KR;

Seungwon Lee, Hwaseong-si, KR;

Seogoo Kang, Seoul, KR;

Juyoung Lim, Seoul, KR;

Jeehoon Han, Hwaseong-si, KR;

Assignee:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Attorney:

Lee IP Law, P.C.

Primary Examiner:

Mouloucoulaye Inoussa

Int. Cl.
CPC ...
H01L 27/11582 (2017.01); H01L 29/51 (2006.01); H01L 29/49 (2006.01); H01L 23/528 (2006.01); H01L 23/522 (2006.01); G11C 16/10 (2006.01); G11C 16/04 (2006.01); G11C 16/26 (2006.01); G11C 11/56 (2006.01); H01L 27/11565 (2017.01); H01L 21/311 (2006.01); H01L 21/28 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); G11C 11/5671 (2013.01); G11C 16/0483 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 27/11565 (2013.01); H01L 29/4916 (2013.01); H01L 29/513 (2013.01); H01L 29/518 (2013.01); H01L 21/31111 (2013.01); H01L 21/31116 (2013.01); H01L 29/40117 (2019.08);
Abstract

A vertical non-volatile memory device includes a channel on a substrate and extending in a first direction perpendicular to an upper surface of the substrate, a first charge storage structure on an outer sidewall of the channel, a second charge storage structure on an inner sidewall of the channel, first gate electrodes spaced apart from each other in the first direction on the substrate, each which surrounds the first charge storage structure, and a second gate electrode on an inner sidewall of the second charge storage structure.

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