The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 13, 2022

Filed:

Apr. 13, 2021
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Wang Xiang, Singapore, SG;

Chia-Ching Hsu, Singapore, SG;

Shen-De Wang, Hsinchu County, TW;

Weichang Liu, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01); H01L 29/66 (2006.01); H01L 27/092 (2006.01); H01L 27/11568 (2017.01); H01L 27/11573 (2017.01); H01L 21/02 (2006.01); H01L 21/28 (2006.01); H01L 29/49 (2006.01); H01L 21/3213 (2006.01); H01L 21/027 (2006.01); H01L 29/78 (2006.01); H01L 29/51 (2006.01); H01L 21/8238 (2006.01); H01L 21/311 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11568 (2013.01); H01L 21/0217 (2013.01); H01L 21/0274 (2013.01); H01L 21/02164 (2013.01); H01L 21/02238 (2013.01); H01L 21/28035 (2013.01); H01L 21/28167 (2013.01); H01L 21/31144 (2013.01); H01L 21/32139 (2013.01); H01L 21/823828 (2013.01); H01L 21/823857 (2013.01); H01L 27/092 (2013.01); H01L 27/11573 (2013.01); H01L 29/40117 (2019.08); H01L 29/4916 (2013.01); H01L 29/513 (2013.01); H01L 29/518 (2013.01); H01L 29/66681 (2013.01); H01L 29/7816 (2013.01);
Abstract

A semiconductor device with integrated memory devices and metal-oxide-semiconductor (MOS) devices, including a substrate with a first area and a second area, multiple double-diffused metal-oxide-semiconductor (DMOS) devices on the first area, wherein the double-diffused metal-oxide-semiconductor (DMOS) device includes a field oxide on the substrate, a first gate dielectric layer adjacent to the field oxide, and a first polysilicon gate on the field oxide and the first gate dielectric layer, and multiple memory units on the second area, wherein the memory unit includes an oxide-nitride-oxide (ONO) tri-layer and a second polysilicon gate on the oxide-nitride-oxide (ONO) tri-layer, wherein a top surface of the second polysilicon gate of the memory unit in the second area and a top surface of the first polysilicon gate of the double-diffused metal-oxide-semiconductor (DMOS) in the first area are on the same level.


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