The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 13, 2022

Filed:

Nov. 12, 2020
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Woon Yik Yong, Singapore, SG;

Andreas Kucher, Villach, AT;

Chia-Yen Lee, Singapore, SG;

Shao Ping Wan, Singapore, SG;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/495 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49575 (2013.01); H01L 24/11 (2013.01); H01L 24/17 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/16227 (2013.01); H01L 2924/014 (2013.01); H01L 2924/12042 (2013.01);
Abstract

An embodiment of a semiconductor package includes a leadframe having leads, a mold compound partly encasing the leadframe so that the leads protrude from the mold compound, a power transistor die attached to the leadframe at a first side of the leadframe, and a driver die attached to the leadframe at a second side of the leadframe opposite the first side so that the power transistor die and the driver die are disposed in a stacked arrangement. The driver die is configured to control the power transistor die. The driver die is in direct electrical communication with the power transistor die only through the leadframe and any interconnects which attach the power transistor die and the driver die to the leadframe. Corresponding methods of manufacturing the semiconductor package are also described.


Find Patent Forward Citations

Loading…