The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 13, 2022

Filed:

Jan. 13, 2021
Applicant:

Shanghai Huali Integrated Circuit Corporation, Shanghai, CN;

Inventors:

Weiwei Ma, Shanghai, CN;

Chao Sun, Shanghai, CN;

Wei Lu, Shanghai, CN;

Xiaolin Xu, Shanghai, CN;

Yamin Cao, Shanghai, CN;

Wei Zhou, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 21/02 (2006.01); H01L 21/8238 (2006.01); H01L 21/78 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823468 (2013.01); H01L 21/0223 (2013.01); H01L 21/02123 (2013.01); H01L 21/823462 (2013.01); H01L 21/823807 (2013.01); H01L 29/7843 (2013.01);
Abstract

The application discloses a method of applying the stress memorization technique in making the semiconductor device which includes: step 1: forming a front gate structure on a silicon wafer having front and back surfaces; step 2: forming sidewalls including a first silicon nitride sidewall, a first silicon nitride layer corresponding to the first silicon nitride sidewall covering a first polysilicon layer on the wafer's back surface; step 3: growing a second silicon nitride layer on the wafer's front surface; step 4: etching the silicon nitride after stress transfer is completed, including: step 41: performing front single-wafer wet etching; step 42: performing batch wet etching to completely remove the second silicon nitride layer and reduces the thickness of the first silicon nitride layer on the back surface; step 5: completing the subsequent process. The application can improve the wafer flatness for improved photolithography for back-end-of-line processes and thereby increasing product yield.


Find Patent Forward Citations

Ma, Weiwei. (2022). Method for making semiconductor device by adopting stress memorization technique (U.S. Patent No. 11443986). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11443986

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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