The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 13, 2022

Filed:

May. 30, 2018
Applicant:

Turun Yliopisto, Turku, FI;

Inventors:

Pekka Laukkanen, Turku, FI;

Mikhail Kuzmin, St. Petersburg, RU;

Jaakko Mäkelä, Turku, FI;

Marjukka Tuominen, Raisio, FI;

Marko Punkkinen, Turku, FI;

Antti Lahti, Turku, FI;

Kalevi Kokko, Turku, FI;

Juha-Pekka Lehtiö, Turku, FI;

Assignee:

TURUN YLIOPISTO, Turku, FI;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/762 (2006.01); H01L 21/02 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 21/7624 (2013.01); H01L 21/02238 (2013.01); H01L 21/02255 (2013.01); H01L 23/3171 (2013.01); H01L 21/0228 (2013.01); H01L 21/02164 (2013.01); H01L 21/02172 (2013.01); H01L 21/02271 (2013.01);
Abstract

A method () for forming a semiconductor structure () comprising a silicon-on-insulator layer structure with crystalline silicon oxide SiOas the insulator material comprises: providing () a crystalline silicon substrate () having a substantially clean deposition surface () in a vacuum chamber; heating () the silicon substrate to an oxidation temperature To in the range of 550 to 1200, 550 to 1000, or 550 to 850° C.; supplying (), while keeping the silicon substrate in the oxidation temperature, with an oxidation pressure Po in the range of 1·10to 1·10mbar in the vacuum chamber, molecular oxygen Ointo the vacuum chamber with an oxygen dose Din the range of 0.1 to 1000 Langmuir; whereby a crystalline silicon oxide layer () with a thickness of at least two molecular layers is formed within the silicon substrate, between a crystalline silicon base layer () and a crystalline silicon top layer ().


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