The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 13, 2022

Filed:

Feb. 12, 2021
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventor:

Takuya Futatsuyama, Yokohama, JP;

Assignee:

Kioxia Corporation, Minato-ku, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 8/00 (2006.01); G11C 8/08 (2006.01); G11C 5/02 (2006.01); G11C 8/14 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/24 (2006.01); G11C 16/26 (2006.01); H01L 27/11575 (2017.01); H01L 27/11582 (2017.01); H01L 27/11573 (2017.01); G11C 8/12 (2006.01); G11C 11/408 (2006.01); H01L 27/11565 (2017.01); G11C 5/06 (2006.01); G11C 7/12 (2006.01);
U.S. Cl.
CPC ...
G11C 8/08 (2013.01); G11C 5/025 (2013.01); G11C 8/12 (2013.01); G11C 8/14 (2013.01); G11C 11/4085 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01); H01L 27/11573 (2013.01); H01L 27/11575 (2013.01); H01L 27/11582 (2013.01); G11C 5/063 (2013.01); G11C 7/12 (2013.01); H01L 27/11565 (2013.01);
Abstract

A semiconductor memory device according to an embodiment includes: a row decoder and a memory cell array including a first block. The first block includes: a first region, a second region adjacent to the first region in the first direction, and a third region configured to connect the first region and the second region. The memory cell array further includes: a first insulating layer buried in a first trench between the first region and the second region and in contact with the third region; a first contact plug provided in the first insulating layer and electrically connected to the row decoder; and a first interconnect configured to connect a selection gate line and the first contact plug.


Find Patent Forward Citations

Loading…