The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 06, 2022

Filed:

Oct. 01, 2021
Applicant:

Nxp Usa, Inc., Austin, TX (US);

Inventors:

Mathieu Vallet, Cannes, FR;

Stefano Dal Toso, Antibes, FR;

Mathieu Périn, Cairon, FR;

Assignee:

NXP USA, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 21/00 (2006.01); H03K 5/156 (2006.01); H03K 21/10 (2006.01); H03K 23/40 (2006.01);
U.S. Cl.
CPC ...
H03K 5/1565 (2013.01); H03K 21/10 (2013.01); H03K 23/40 (2013.01);
Abstract

A duty cycle correction circuit (DCCC) for a multi-modulus frequency divider, the DCCC comprising: a corrector chain comprising a plurality of flip-flops each configured to receive one of the internal signals; and at least one delay selection logic element, each configured to receive an output signal from different ones of the flip-flops and the output of each delay selection logic element is based on the received output signal and the division factor; the DCCC is configured such that: a first state change in its output signal is defined by a transition to a first logic state of one of the internal signals; and a second state change in its output signal is based on a transition to a second logic state of one of the internal signals after a delay period, wherein the duty cycle of the output signal is based on the delay period.


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