The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 06, 2022

Filed:

Apr. 16, 2020
Applicant:

Nexchip Semiconductor Co., Ltd, Anhui, CN;

Inventors:

Zhongxiang Ma, Anhui, CN;

Ching-Ming Lee, Anhui, CN;

Po-Hua Kung, Anhui, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823462 (2013.01); H01L 21/823481 (2013.01); H01L 27/088 (2013.01); H01L 29/0649 (2013.01); H01L 29/42364 (2013.01);
Abstract

The present disclosure provides a method for manufacturing semiconductor device and a semiconductor device formed using same. The method includes: preparing a substrate; forming a pad oxide layer and a barrier layer on the substrate, the barrier layer is disposed on the pad oxide layer; forming a plurality of shallow trench isolation structures in the substrate to form multiple regions in the substrate; removing a part of the barrier layer to form a recess, the recess is set in any one of the multiple regions, and a region directly below the recess is defined as a high voltage device region; and forming a gate oxide layer in the recess, and removing the barrier layer. The method provided in the present disclosure simplifies the manufacturing process and reduces the production costs.


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