The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 06, 2022
Filed:
Dec. 27, 2019
Intel Corporation, Santa Clara, CA (US);
Eliezer Weissmann, Haifa, IL;
Omer Barak, Modi'in, IL;
Rajshree Chabukswar, Sunnyvale, CA (US);
Russell Fenger, Beaverton, OR (US);
Eugene Gorbatov, Hillsboro, OR (US);
Monica Gupta, Hillsboro, OR (US);
Julius Mandelblat, Haifa, IL;
Nir Misgav, Santa Clara, CA (US);
Efraim Rotem, Haifa, IL;
Ahmad Yasin, Haifa, IL;
Intel Corporation, Santa Clara, CA (US);
Abstract
An apparatus and method for intelligently scheduling threads across a plurality of logical processors. For example, one embodiment of a processor comprises: a plurality of logical processors including comprising one or more of a first logical processor type and a second logical processor type, the first logical processor type associated with a first core type and the second logical processor type associated with a second core type; a scheduler to schedule a plurality of threads for execution on the plurality of logical processors in accordance with performance data associated with the plurality of threads; wherein if the performance data indicates that a new thread should be executed on a logical processor of the first logical processor type, but all logical processors of the first logical processor type are busy, the scheduler to determine whether to migrate a second thread from the logical processors of the first logical processor type to a logical processor of the second logical processor type based on an evaluation of first and second performance values associated with execution of the first thread on the first or second logical processor types, respectively, and further based on an evaluation of third and fourth performance values associated with execution of the second thread on the first or second logical processor types, respectively.