The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 06, 2022

Filed:

Jul. 24, 2017
Applicants:

Barcelona Supercomputing Center, Barcelona, ES;

Universitat Politecnica DE Catalunya, Barcelona, ES;

Inventors:

Xubin Tan, Barcelona, ES;

Carlos Alvarez Martinez, Barcelona, ES;

Jaume Bosch Pons, Barcelona, ES;

Daniel Jimenez Gonzalez, Barcelona, ES;

Mateo Valero Cortes, Barcelona, ES;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/48 (2006.01); G06F 9/30 (2018.01); G06F 9/50 (2006.01); G06F 9/52 (2006.01); G06F 9/54 (2006.01); G06F 9/4401 (2018.01);
U.S. Cl.
CPC ...
G06F 9/4881 (2013.01); G06F 9/3009 (2013.01); G06F 9/30047 (2013.01); G06F 9/4405 (2013.01); G06F 9/5016 (2013.01); G06F 9/5027 (2013.01); G06F 9/524 (2013.01); G06F 9/544 (2013.01); G06F 9/546 (2013.01); G06F 2209/503 (2013.01); G06F 2209/5011 (2013.01); G06F 2209/5018 (2013.01);
Abstract

Hardware acceleration of task dependency management in parallel computing, wherein solutions are proposed for hardware-based dependency management to support nested tasks, resolve system deadlocks as a result of memory full conditions in the dedicated hardware memory and synergetic operation of software runtime and hardware acceleration to solve otherwise unsolvable deadlocks when nested tasks are processed. Buffered asynchronous communication of larger data exchange are introduced, requiring less support from multi-core processor elements as opposed to standard access through the multi-core processor elements. A hardware acceleration processor may be implemented in the same silicon die as the multi-core processor for achieving gains in performance, fabrication cost reduction and energy consumption saving during operation.


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