The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 30, 2022

Filed:

Mar. 10, 2021
Applicants:

Kabushiki Kaisha Toshiba, Tokyo, JP;

Toshiba Electronic Devices & Storage Corporation, Tokyo, JP;

Inventor:

Toshifumi Nishiguchi, Hakusan Ishikawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 29/417 (2006.01); H01L 29/10 (2006.01); H01L 29/423 (2006.01); H01L 29/08 (2006.01); H01L 29/739 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7813 (2013.01); H01L 29/0869 (2013.01); H01L 29/1095 (2013.01); H01L 29/41741 (2013.01); H01L 29/4236 (2013.01); H01L 29/66348 (2013.01); H01L 29/66734 (2013.01); H01L 29/7397 (2013.01);
Abstract

According to one embodiment, a semiconductor device includes a first electrode, first and third semiconductor regions of a first conductivity type, second and fourth semiconductor regions of a second conductivity type, a gate electrode and a second electrode. The third semiconductor region is disposed on one portion of the second semiconductor region. The fourth semiconductor region is disposed on another portion of the second semiconductor region, is positioned below the third semiconductor region. The second electrode includes first and second portions separated from each other and allowing the fourth semiconductor region to be positioned therebetween, and the third portion disposed on the first and second portions and arranged with the third semiconductor region. The first, second, and third portions are in contact with the fourth semiconductor region.


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