The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 30, 2022

Filed:

Jun. 11, 2020
Applicant:

SK Hynix Inc., Icheon-si, KR;

Inventors:

Chaesung Lee, Icheon-si, KR;

Jonghoon Kim, Suwon-si, KR;

Bokkyu Choi, Yongin-si, KR;

Kijun Sung, Cheongju-si, KR;

Assignee:

SK hynix Inc., Icheon-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 2225/06548 (2013.01); H01L 2225/06562 (2013.01); H01L 2225/06586 (2013.01);
Abstract

A semiconductor package may include: a chip stack including a plurality of semiconductor chips stacked in a vertical direction; vertical interconnectors, each having first ends that are connected to the plurality of semiconductor chips, respectively, and extending in the vertical direction; a molding layer covering the chip stack and the vertical interconnectors while exposing second ends of the vertical interconnectors; landing pads formed over one surface of the molding layer to be in contact with the second ends of the vertical interconnectors, respectively, wherein the landing pads are conductive and overlap the first ends of the vertical interconnectors, respectively; and a package redistribution layer electrically connected to the vertical interconnectors through the landing pads.


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