The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 30, 2022

Filed:

Dec. 30, 2020
Applicant:

Alpha and Omega Semiconductor International Lp, Sunnyvale, CA (US);

Inventors:

Yan Xun Xue, Los Gatos, CA (US);

Madhur Bobde, Sunnyvale, CA (US);

Long-Ching Wang, Cupertino, CA (US);

Bo Chen, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/683 (2006.01); H01L 23/00 (2006.01); H01L 21/78 (2006.01);
U.S. Cl.
CPC ...
H01L 24/97 (2013.01); H01L 21/6836 (2013.01); H01L 21/78 (2013.01); H01L 24/32 (2013.01); H01L 2221/68327 (2013.01); H01L 2221/68368 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/95001 (2013.01);
Abstract

A semi-wafer level packaging method comprises the steps of providing a wafer; grinding a back side of the wafer; forming a metallization layer; removing a peripheral ring; bonding a first tape; applying a dicing process; bonding a second tape; removing the first tape; bonding a supporting structure; bonding a third tape; removing the second tape; and applying a singulation process. A semi-wafer level packaging method comprises the steps of providing a wafer; attaching a carrier wafer to the wafer; grinding a back side of the wafer; forming a metallization layer; applying a dicing process; bonding a supporting structure; removing the carrier wafer; bonding a tape; and applying a singulation process.


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