The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 30, 2022

Filed:

Apr. 06, 2021
Applicant:

Nxp Usa, Inc., Austin, TX (US);

Inventors:

Humayun Kabir, Gilbert, AZ (US);

Michele Lynn Miera, Gilbert, AZ (US);

Charles John Lessard, Gilbert, AZ (US);

Ibrahim Khalil, Gilbert, AZ (US);

Assignee:

NXP USA, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); H01L 21/768 (2006.01); H01L 23/552 (2006.01); H01L 23/535 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 23/552 (2013.01); H01L 21/768 (2013.01); H01L 23/5225 (2013.01); H01L 23/535 (2013.01); H01L 29/78 (2013.01);
Abstract

A transistor includes a semiconductor substrate having first and second terminals. An interconnect structure, on an upper surface of the substrate, is formed of layers of dielectric material and electrically conductive material. The conductive material includes a first pillar connected with the first terminal, a second pillar connected with the second terminal, and a shield system between the first and second pillars. The shield system includes forked structures formed in at least two conductive layers of the interconnect structure and at least partially surrounding segments of the second pillar. The shield system may additionally include shield traces formed in a first conductive layer positioned between gate fingers and the first pillars and/or the shield system may include shield runners that are located in an electrically conductive layer that is below a topmost electrically conductive layer with the first pillar being connected to a runner in the topmost conductive layer.


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