The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 30, 2022
Filed:
Sep. 29, 2020
Shenzhen Unionmemory Information System Limited, Shenzhen, CN;
Jian Zuo, Shenzhen, CN;
Yuanyuan Feng, Shenzhen, CN;
Zhiyuan Leng, Shenzhen, CN;
Jintao Gan, Shenzhen, CN;
Weiliang Wang, Shenzhen, CN;
Zongming Jia, Shenzhen, CN;
SHENZHEN UNIONMEMORY INFORMATION SYSTEM LIMITED, Guangdong, CN;
Abstract
A method of reducing FTL address mapping space, including: S1, obtaining a mpa and an offset according to a logical page address; S2, determining whether the mpa is hit in a cache; S3, determining whether a NAND is written into the mpa; S4, performing a nomap load operation, and returning an invalid mapping; S5, performing a map load operation; S6, directly searching a mpci representing a position of the mpa in the cache and searching a physical page address gppa with reference to the offset; S7, determining whether a mapping from a logical address to a physical address needs to be modified; S8, modifying a mapping table corresponding to the mpci in the cache, and marking a mp corresponding to the mpci as a dirty mp; S9, determining whether to trigger a condition of writing the mp into the NAND; and S10, writing the dirty mp into the NAND.