The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 23, 2022

Filed:

Oct. 14, 2020
Applicant:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

Inventor:

Richard T. Schultz, Fort Collins, CO (US);

Assignee:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/00 (2006.01); H01L 29/423 (2006.01); H01L 21/768 (2006.01); H01L 23/535 (2006.01); H01L 27/02 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 29/4238 (2013.01); H01L 21/76895 (2013.01); H01L 23/535 (2013.01); H01L 27/0207 (2013.01); H01L 29/42392 (2013.01); H01L 29/6656 (2013.01); H01L 29/66666 (2013.01); H01L 29/78642 (2013.01); H01L 29/78696 (2013.01);
Abstract

A system and method for laying out power grid connections for standard cells are described. In various implementations, gate metal is placed over non-planar vertical conducting structures, which are used to form non-planar devices (transistors). Gate contacts connect gate metal to gate extension metal (GEM) above the gate metal. GEM is placed above the gate metal and makes a connection with gate metal through the one or more gate contacts. Gate extension contacts are formed on the GEM above the active regions. Similar to gate contacts, gate extension contacts are formed with a less complex fabrication process than using a self-aligned contacts process. Gate extension contacts connect GEM to an interconnect layer such as a metal zero layer. Gate extension contacts are aligned vertically with one of the non-planar vertical conducting structures. Therefore, in an implementation, one or more gate extension contacts are located above the active region.


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