The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 23, 2022

Filed:

Dec. 21, 2017
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Denzil S. Frost, Boise, ID (US);

Tuman Earl Allen, III, Kuna, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/24 (2006.01); H01L 23/528 (2006.01); H01L 45/00 (2006.01); H01L 27/10 (2006.01);
U.S. Cl.
CPC ...
H01L 27/2463 (2013.01); H01L 23/528 (2013.01); H01L 27/101 (2013.01); H01L 27/2409 (2013.01); H01L 27/2481 (2013.01); H01L 45/1233 (2013.01); H01L 45/1608 (2013.01); H01L 45/1675 (2013.01);
Abstract

A method of forming an array of memory cells comprises forming an elevationally inner tier of memory cells comprising spaced inner tier lower first conductive lines, spaced inner tier upper second conductive lines, and programmable material of individual inner tier memory cells elevationally between the inner tier first lines and the inner tier second lines where such cross. First insulative material is formed laterally between the inner tier second lines to have respective elevationally outermost surfaces that are lower than elevationally outermost surfaces of immediately laterally-adjacent of the inner tier second lines. Second insulative material is formed elevationally over the first insulative material and laterally between the inner tier second lines. The second insulative material is of different composition from that of the first insulative material. An elevationally outer tier of memory cells is formed to comprise spaced outer tier lower first conductive lines, spaced outer tier upper second conductive lines, and programmable material of individual outer tier memory cells elevationally between the outer tier first lines and the outer tier second lines where such cross. Arrays of memory cells independent of method of manufacture are disclosed.


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