The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 23, 2022

Filed:

Apr. 02, 2020
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Jung-Hwan Kim, Seoul, KR;

Sunggil Kim, Yongin-si, KR;

Dongkyum Kim, Suwon-si, KR;

Seulye Kim, Seoul, KR;

Ji-Hoon Choi, Seongnam-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 27/11582 (2017.01); H01L 29/04 (2006.01); H01L 27/11565 (2017.01); H01L 29/792 (2006.01); H01L 27/11573 (2017.01); H01L 29/423 (2006.01); H01L 27/1157 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 27/1157 (2013.01); H01L 27/11565 (2013.01); H01L 27/11573 (2013.01); H01L 29/04 (2013.01); H01L 29/42344 (2013.01); H01L 29/7926 (2013.01);
Abstract

A three-dimensional semiconductor memory device is disclosed. The device may include a first source conductive pattern comprising a polycrystalline material including first crystal grains on a substrate, the substrate may comprising a polycrystalline material including second crystal grains, a grain size of the first crystal grains being smaller than a grain size of the second crystal grains, a stack including a plurality of gate electrodes, the plurality of gates stacked on the first source conductive pattern, and a vertical channel portion penetrating the stack and the first source conductive pattern, and the vertical channel portion being in contact with a side surface of the first source conductive pattern.


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