The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 23, 2022
Filed:
Dec. 13, 2019
Applicant:
Winbond Electronics Corp., Taichung, TW;
Inventors:
Assignee:
WInbond Electronics Corp., Taichung, TW;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 27/11521 (2017.01); H01L 27/11531 (2017.01); H01L 29/06 (2006.01); H01L 29/788 (2006.01); H01L 21/762 (2006.01); H01L 21/28 (2006.01); H01L 29/78 (2006.01); H01L 21/3213 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11521 (2013.01); H01L 21/76224 (2013.01); H01L 27/11531 (2013.01); H01L 29/0653 (2013.01); H01L 29/40114 (2019.08); H01L 29/42324 (2013.01); H01L 29/66598 (2013.01); H01L 29/66825 (2013.01); H01L 29/7833 (2013.01); H01L 29/7883 (2013.01); H01L 21/3213 (2013.01);
Abstract
A semiconductor device and a manufacturing method of the same are provided. The semiconductor device includes a substrate, a plurality of floating gates, a tunneling dielectric layer, a plurality of control gates, and an ONO layer. The floating gates are located on the substrate, and the tunneling dielectric layer is located between the substrate and each of the floating gates. The control gates are located on the floating gates, and the ONO layer is located on two sidewalls of each of the control gates and between each of the control gates and each of the floating gates.