The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 23, 2022

Filed:

Nov. 23, 2020
Applicant:

Yield Microelectronics Corp., Chu-Pei, TW;

Inventors:

Wen-Chien Huang, Chu-Pei, TW;

Yu Ting Huang, Chu-Pei, TW;

Chi Pei Wu, Chu-Pei, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/52 (2006.01); H01L 21/82 (2006.01); H01L 27/112 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11206 (2013.01);
Abstract

A small-area and low-voltage anti-fuse element comprises four first gate dielectric layers each two symmetrically distributed; and an anti-fuse gate formed on the first gate dielectric layers, wherein four corners of the anti-fuse gate respectively overlap corners of the first gate dielectric layers, which are closest to the anti-fuse gate; each of the four corners of the anti-fuse gate is fabricated to have at least one sharp angle. The present invention is characterized in that four first gate dielectric layers share an anti-fuse gate and that the sharp angle has a higher density of charges. Therefore, the present invention can greatly reduce the size of elements, lower the voltage required to puncture the first gate dielectric layer, and decrease the power consumption. The present invention also discloses a small-area and low-voltage anti-fuse array.


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