The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 23, 2022

Filed:

Nov. 10, 2020
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Kuo-Chiang Tsai, Hsinchu, TW;

Jyh-Huei Chen, Hsinchu, TW;

Jye-Yen Cheng, Taichung, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/538 (2006.01); H01L 29/417 (2006.01); H01L 21/768 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5384 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 23/53257 (2013.01); H01L 29/4175 (2013.01);
Abstract

A method of fabricating an integrated circuit device is provided. The method includes depositing a first dielectric layer over a semiconductor substrate and forming first and second via contacts in the first dielectric layer and extending below a bottom surface of the first dielectric layer. The method also includes etching back the first dielectric layer to expose upper portions of the first and second via contacts. The method further includes depositing an etch stop layer conformally on the upper portions of the first and second via contacts and on the first dielectric layer. In addition, the method includes depositing a second dielectric layer on the etch stop layer and forming first and second metal lines in the second dielectric layer to be electrically connected to the first via contact and the second via contact, respectively.


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