The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 23, 2022
Filed:
Jan. 13, 2021
Applicant:
Applied Materials, Inc., Santa Clara, CA (US);
Inventors:
Qintao Zhang, Mt Kisco, NY (US);
Wei Zou, Lexington, MA (US);
Hans-Joachim L. Gossmann, Summit, NJ (US);
Assignee:
Applied Materials, Inc., Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/28 (2006.01); H01L 29/66 (2006.01); H01L 21/04 (2006.01); H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
H01L 21/047 (2013.01); H01L 21/28185 (2013.01); H01L 21/823468 (2013.01); H01L 29/66734 (2013.01);
Abstract
Disclosed herein are methods for reducing MOSFET trench sidewall surface roughness. In some embodiments, a method includes providing a device structure including a well formed in an epitaxial layer, forming a plurality of trenches through the well and the epitaxial layer, and implanting the device structure to form a treated layer along a sidewall of just an upper portion of the device structure within each of the plurality of trenches. The method may further include etching the device structure to remove the treated layer.