The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 23, 2022

Filed:

Mar. 15, 2021
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventors:

Akiyuki Murayama, Koto Tokyo, JP;

Kikuko Sugimae, Yokohama Kanagawa, JP;

Katsuya Nishiyama, Yokohama Kanagawa, JP;

Motohiko Fujimatsu, Yokohama Kanagawa, JP;

Noboru Shibata, Kawasaki Kanagawa, JP;

Assignee:

KIOXIA CORPORATION, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/34 (2006.01); G11C 16/34 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/24 (2006.01); G11C 16/30 (2006.01);
U.S. Cl.
CPC ...
G11C 16/3459 (2013.01); G11C 16/0425 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01); G11C 16/30 (2013.01);
Abstract

A semiconductor memory device includes first and second memory string including first and second memory cell, respectively, and first and second bit line connected to first and second memory string, respectively. In a first program operation, a first bit line voltage is supplied to the first and the second bit line. In a second program operation, a second bit line voltage larger than the first bit line voltage or a third bit line voltage larger than the second bit line voltage is supplied to the first and the second bit line. In a third program operation, the second and the third bit line voltage is supplied to the first and the second bit line, respectively. In a fourth program operation, the third and the second bit line voltage is supplied to the first and the second bit line, respectively.


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