The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 23, 2022

Filed:

Aug. 22, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Deepak Samuel Kirubakaran, Hillsboro, OR (US);

Vijay Dhanraj, Beaverton, OR (US);

Russell Jerome Fenger, Beaverton, OR (US);

Hisham Abu-Salah, Majdal Shams, IL;

Eliezer Weissmann, Haifa, IL;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/32 (2019.01); G06F 9/46 (2006.01); G06F 9/455 (2018.01); G06F 9/48 (2006.01); G06F 1/3296 (2019.01); G06F 9/50 (2006.01); G06F 1/3234 (2019.01); G06F 9/38 (2018.01); G06F 1/3203 (2019.01); G06F 1/3287 (2019.01); G06F 1/329 (2019.01); G06F 11/34 (2006.01);
U.S. Cl.
CPC ...
G06F 9/4831 (2013.01); G06F 1/3296 (2013.01); G06F 1/3203 (2013.01); G06F 1/329 (2013.01); G06F 1/3243 (2013.01); G06F 1/3287 (2013.01); G06F 9/3851 (2013.01); G06F 9/3857 (2013.01); G06F 9/5027 (2013.01); G06F 9/5077 (2013.01); G06F 11/3423 (2013.01); G06F 2209/5018 (2013.01); G06F 2209/5022 (2013.01);
Abstract

A data processing system with technology for dynamically grouping threads includes a machine-readable medium and first and second cores, each with multiple logical processors (LPs). The system also comprises an operating system which, when executed, enables the system to select an LP to receive a new low-priority thread and to assign the new low-priority thread to the selected LP. The operation of selecting an LP to receive the new low-priority thread comprises, when the first core has multiple idle LPs, automatically determining whether the second core has an idle LP and a busy LP that is executing a current low-priority thread. In response to determining that the second core has an idle LP and a busy LP that is executing a current low-priority thread, the system automatically selects the idle LP in the second core to receive the new low-priority thread. Other embodiments are described and claimed.


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