The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 16, 2022

Filed:

Aug. 06, 2019
Applicant:

Finisar Corporation, Sunnyvale, CA (US);

Inventors:

Jianwei Mu, Pleasanton, CA (US);

Frank Lei Ding, Milpitas, CA (US);

Tao Wu, Union City, CA (US);

Hongyu Deng, Saratoga, CA (US);

Maziar Amirkiai, Sunnyvale, CA (US);

Assignee:

II-VI DELAWARE, INC., Wilmington, DE (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01S 5/02325 (2021.01); H01L 23/498 (2006.01); H01S 5/024 (2006.01); H01L 23/34 (2006.01); H01L 21/48 (2006.01); H01S 5/0233 (2021.01); H01S 5/0235 (2021.01);
U.S. Cl.
CPC ...
H01S 5/02325 (2021.01); H01L 21/4857 (2013.01); H01L 23/345 (2013.01); H01L 23/49822 (2013.01); H01L 23/49838 (2013.01); H01S 5/024 (2013.01); H01S 5/0233 (2021.01); H01S 5/0235 (2021.01); H01S 5/02453 (2013.01);
Abstract

A chip may include a first substantially planar isolation layer with a first surface and a second surface opposite the first surface. The chip may include a first substantially planar conduction layer with a first surface positioned adjacent to the second surface of the first isolation layer and a second surface opposite the first surface. The chip may include a second substantially planar isolation layer with a first surface positioned adjacent to the second surface of the first conduction layer and a second surface opposite the first surface. The chip may include a second conduction layer etched on the second surface of the second isolation layer. The second conduction layer may include an anode trace, a cathode trace, and an optical transmitter positioned on the cathode trace. The chip may include one or more vias through the second isolation layer electrically coupling the anode trace with the first conduction layer.


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