The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 16, 2022

Filed:

Feb. 15, 2021
Applicant:

Stmicroelectronics (Crolles 2) Sas, Crolles, FR;

Inventors:

Edoardo Brezza, Grenoble, FR;

Alexis Gauthier, Meylan, FR;

Fabien Deprat, Chambery, FR;

Pascal Chevalier, Chapareillan, FR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/737 (2006.01); H01L 21/8249 (2006.01); H01L 29/08 (2006.01); H01L 29/417 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7371 (2013.01); H01L 21/8249 (2013.01); H01L 29/0817 (2013.01); H01L 29/41708 (2013.01); H01L 29/66318 (2013.01);
Abstract

A method of making a bipolar transistor includes forming a stack of a first, second, third and fourth insulating layers on a substrate. An opening is formed in the stack to reach the substrate. An epitaxial process forms the collector of the transistor on the substrate and selectively etches an annular opening in the third layer. The intrinsic part of the base is then formed by epitaxy on the collector, with the intrinsic part being separated from the third layer by the annular opening. The junction between the collector and the intrinsic part of the base is surrounded by the second layer. The emitter is formed on the intrinsic part and the third layer is removed. A selective deposition of a semiconductor layer on the second layer and in direct contact with the intrinsic part forms the extrinsic part of the base.


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