The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 16, 2022

Filed:

Jun. 07, 2018
Applicant:

Nissin Electric Co., Ltd., Kyoto, JP;

Inventors:

Daisuke Matsuo, Kyoto, JP;

Yasunori Ando, Kyoto, JP;

Yoshitaka Setoguchi, Kyoto, JP;

Shigeaki Kishida, Kyoto, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); C23C 14/08 (2006.01); C23C 14/34 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66742 (2013.01); C23C 14/08 (2013.01); C23C 14/34 (2013.01);
Abstract

Provided is a method for producing a thin film transistor that has a gate electrode, a gate insulating layer, an oxide semiconductor layer, a source electrode and a drain electrode on a substrate. This method for producing a thin film transistor includes a step for forming the oxide semiconductor layer on the gate insulating layer by performing sputtering on a target with plasma. The step for forming the oxide semiconductor layer includes: a first film formation step in which only argon is supplied as a sputtering gas to perform sputtering; and a second film formation step in which a mixed gas of argon and oxygen is supplied as the sputtering gas to perform sputtering. A bias voltage applied to the target is a negative voltage of −1 kV or higher.


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