The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 16, 2022
Filed:
Feb. 04, 2021
Texas Instruments Incorporated, Dallas, TX (US);
Peng Li, Chengdu, CN;
Ya ping Chen, Chengdu, CN;
Yunlong Liu, Chengdu, CN;
Hong Yang, Richardson, TX (US);
Shengpin Yang, Chengdu, CN;
Jing Hu, Chengdu, CN;
Chao Zhuang, Chengdu, CN;
TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US);
Abstract
A method () of fabricating a semiconductor device includes etching () a group of trenches in a semiconductor surface layer of a substrate. The group of trenches includes an outermost trench that has a first width and remaining trenches of the group of trenches have a second width that is less than the first width. The outermost trench is formed at an edge of the group of trenches. A dielectric liner is formed () in the group of trenches and the dielectric liner is etched () in an upper portion of the group of trenches to remove a partial thickness of the dielectric liner. A full thickness of the dielectric liner is maintained in a lower portion of the group of trenches. The group of trenches is filled () with a polysilicon layer.