The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 09, 2022

Filed:

Sep. 13, 2018
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Huichu Liu, Santa Clara, CA (US);

Sasikanth Manipatruni, Portland, OR (US);

Daniel Morris, Hillsboro, OR (US);

Kaushik Vaidyanathan, Santa Clara, CA (US);

Tanay Karnik, Portland, OR (US);

Ian Young, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); H01L 43/04 (2006.01); H01L 43/06 (2006.01); G11C 11/16 (2006.01); G11C 11/18 (2006.01); H01L 43/10 (2006.01);
U.S. Cl.
CPC ...
H01L 43/04 (2013.01); G11C 11/161 (2013.01); G11C 11/165 (2013.01); G11C 11/18 (2013.01); H01L 43/065 (2013.01); H01L 43/10 (2013.01);
Abstract

An apparatus is provided which comprises a full adder including magnetoelectric material and spin orbit material. In some embodiments, the adder includes: a 3-bit carry generation structure and a multi-bit sum generation structure coupled to the 3-bit carry generation structure. In some embodiments, the 3-bit carry generation structure includes at least three cells comprising magnetoelectric material and spin orbit material, wherein the 3-bit carry generation structure is to perform a minority logic operation on first, second, and third inputs to generate a carry output. In some embodiments, the multi-bit sum generation structure includes at least four cells comprising magnetoelectric material and spin orbit material, wherein the multi-bit sum generation structure is to perform a minority logic operation on the first, second, and third inputs and the carry output to generate a sum output.


Find Patent Forward Citations

Loading…