The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 09, 2022

Filed:

Sep. 10, 2020
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Srinivas Pulugurtha, Boise, ID (US);

Litao Yang, Boise, ID (US);

Haitao Liu, Boise, ID (US);

Kamal M. Karda, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/786 (2006.01); H01L 27/11514 (2017.01); H01L 29/49 (2006.01); H01L 27/108 (2006.01); H01L 29/51 (2006.01);
U.S. Cl.
CPC ...
H01L 29/78642 (2013.01); H01L 27/10808 (2013.01); H01L 27/11514 (2013.01); H01L 29/4966 (2013.01); H01L 29/517 (2013.01); H01L 29/7869 (2013.01);
Abstract

Some embodiments include integrated memory. The integrated memory includes a first series of first conductive structures and a second series of conductive structures. The first conductive structures extend along a first direction. The second conductive structures extend along a second direction which crosses the first direction. Pillars of semiconductor material extend upwardly from the first conductive structures. Each of the pillars includes a lower source/drain region, an upper source/drain region, and a channel region between the lower and upper source/drain regions. The lower source/drain regions are coupled with the first conductive structures. Insulative material is adjacent sidewall surfaces of the pillars. The insulative material includes ZrO, where x is a number greater than 0. The second conductive structures include gating regions which are spaced from the channel regions by at least the insulative material. Storage elements are coupled with the upper source/drain regions.


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