The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 09, 2022

Filed:

Jul. 08, 2020
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Chanho Kim, Seoul, KR;

Daeseok Byeon, Seongnam-si, KR;

Dongku Kang, Seongnam-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11573 (2017.01); H01L 27/11519 (2017.01); H01L 27/11524 (2017.01); H01L 27/11556 (2017.01); H01L 27/11529 (2017.01); H01L 21/768 (2006.01); H01L 27/1157 (2017.01); H01L 27/11582 (2017.01); H01L 23/535 (2006.01); H01L 27/11565 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11573 (2013.01); H01L 21/76805 (2013.01); H01L 21/76895 (2013.01); H01L 23/535 (2013.01); H01L 27/1157 (2013.01); H01L 27/11519 (2013.01); H01L 27/11524 (2013.01); H01L 27/11529 (2013.01); H01L 27/11556 (2013.01); H01L 27/11565 (2013.01); H01L 27/11582 (2013.01);
Abstract

An integrated circuit (IC) device includes a peripheral circuit structure, a memory stack including a plurality of gate lines overlapping the peripheral circuit structure in a vertical direction on the peripheral circuit structure, an upper substrate between the peripheral circuit structure and the memory stack, the upper substrate including a through hole positioned below a memory cell region of the memory stack, a word line cut region extending lengthwise in a first lateral direction across the memory stack and the through hole, and a common source line located in the word line cut region, the common source line including a first portion extending lengthwise in the first lateral direction on the upper substrate and a second portion integrally connected to the first portion, the second portion penetrating the upper substrate through the through hole from an upper portion of the upper substrate and extending into the peripheral circuit structure.


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