The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 09, 2022

Filed:

Apr. 16, 2020
Applicant:

Advanced Semiconductor Engineering, Inc., Kaohsiung, TW;

Inventors:

Ian Hu, Kaohsiung, TW;

Shin-Luh Tarng, Kaohsiung, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/538 (2006.01); H01L 21/48 (2006.01); H01L 21/50 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5386 (2013.01); H01L 21/486 (2013.01); H01L 21/50 (2013.01); H01L 23/5384 (2013.01); H01L 23/5389 (2013.01);
Abstract

A substrate, a semiconductor package device and a method of manufacturing a semiconductor device package are provided. The substrate includes a low density wiring structure, a first middle density wiring structure and high density wiring structure. The first middle density wiring structure is electrically connected to the low density wiring structure. The high density wiring structure is electrically connected to the low density wiring structure. The high density wiring structure and the first middle density wiring structure are disposed side by side. A line space of a circuit layer of the low density wiring structure is greater than a line space of a circuit layer of the first middle density wiring structure. The line space of the circuit layer of the first middle density wiring structure is greater than a line space of a circuit layer of the high density wiring structure.


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