The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 09, 2022

Filed:

Dec. 27, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Ranjith Kumar, Beaverton, OR (US);

Srinivasa Chaitanya Gadigatla, Hillsboro, OR (US);

Tamanna Husain, El Dorado Hills, CA (US);

Abhinand Ramakrishnan, Folsom, CA (US);

James Graeber, Folsom, CA (US);

Kohinoor Basu, San Jose, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/39 (2020.01); G06F 30/392 (2020.01); G06F 30/394 (2020.01); H01L 27/02 (2006.01); G06F 111/20 (2020.01); G06F 119/12 (2020.01);
U.S. Cl.
CPC ...
G06F 30/392 (2020.01); G06F 30/394 (2020.01); H01L 27/0207 (2013.01); G06F 2111/20 (2020.01); G06F 2119/12 (2020.01);
Abstract

An integrated circuit structure includes a first metal level comprising a first plurality of interconnect lines along a first direction. A cell is on at least the first metal level, the cell having a pin comprising more than two of the first plurality of interconnect lines. A second metal level comprising a second plurality of interconnect lines overlays the first metal level, where the second plurality of interconnect lines is along a second direction. Two or more vias are on at least one of the second plurality of interconnect lines to connect to the pin.


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