The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 09, 2022
Filed:
Jan. 28, 2021
Intel Corporation, Santa Clara, CA (US);
Vikranth Vemulapalli, Folsom, CA (US);
Lakshminarayanan Striramassarma, Folsom, CA (US);
Mike MacPherson, Portland, OR (US);
Aravindh Anantaraman, Folsom, CA (US);
Ben Ashbaugh, Folsom, CA (US);
Murali Ramadoss, Folsom, CA (US);
William B. Sadler, Folsom, CA (US);
Jonathan Pearce, Hillsboro, OR (US);
Scott Janus, Loomis, CA (US);
Brent Insko, Portland, OR (US);
Vasanth Ranganathan, El Dorado Hills, CA (US);
Kamal Sinha, Rancho Cordova, CA (US);
Arthur Hunter, Jr., Cameron Park, CA (US);
Prasoonkumar Surti, Folsom, CA (US);
Nicolas Galoppo von Borries, Portland, OR (US);
Joydeep Ray, Folsom, CA (US);
Abhishek R. Appu, El Dorado Hills, CA (US);
ElMoustapha Ould-Ahmed-Vall, Chandler, AZ (US);
Altug Koker, El Dorado Hills, CA (US);
Sungye Kim, Folsom, CA (US);
Subramaniam Maiyuran, Gold River, CA (US);
Valentin Andrei, San Jose, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Embodiments are generally directed to data prefetching for graphics data processing. An embodiment of an apparatus includes one or more processors including one or more graphics processing units (GPUs); and a plurality of caches to provide storage for the one or more GPUs, the plurality of caches including at least an L1 cache and an L3 cache, wherein the apparatus to provide intelligent prefetching of data by a prefetcher of a first GPU of the one or more GPUs including measuring a hit rate for the L1 cache; upon determining that the hit rate for the L1 cache is equal to or greater than a threshold value, limiting a prefetch of data to storage in the L3 cache, and upon determining that the hit rate for the L1 cache is less than a threshold value, allowing the prefetch of data to the L1 cache.