The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 02, 2022

Filed:

Jan. 15, 2020
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Cornelius Brown Peethala, Slingerlands, NY (US);

Kedari Matam, Albany, NY (US);

Chih-Chao Yang, Glenmont, NY (US);

Theo Standaert, Clifton Park, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76865 (2013.01); H01L 21/7684 (2013.01); H01L 21/76802 (2013.01); H01L 21/76834 (2013.01); H01L 21/76849 (2013.01); H01L 21/76852 (2013.01); H01L 21/76856 (2013.01); H01L 21/76877 (2013.01); H01L 21/76883 (2013.01); H01L 23/5226 (2013.01); H01L 23/5329 (2013.01); H01L 23/53238 (2013.01);
Abstract

Techniques are provided to fabricate metal interconnects using liner planarization-free process flows. A sacrificial layer is formed on a dielectric layer, and the sacrificial and dielectric layers are patterned to form an opening in the dielectric layer. A conformal liner layer is deposited, and a metal layer deposited to form a metal interconnect in the opening. An overburden portion of the metal layer is planarized to expose an overburden portion of the liner layer. A first wet etch is performed to selectively remove the overburden portion of the liner layer. A second wet etch process is performed to selectively remove the sacrificial layer, resulting in extended portions of the liner layer and the metal interconnect extending above a surface of the dielectric layer. A dielectric capping layer is formed to cover the sidewall and upper surfaces of the extended portions of the liner layer and the metal interconnect.


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