Non-volatile memory with multiple wells for word line switch transistors

Abstract

A non-volatile memory includes a non-volatile memory array comprising blocks of non-volatile memory cells, bit lines connected to the memory cells and word lines connected to the memory cells. Word line switch transistors connect the word lines to voltage sources. The word line switch transistors are positioned in triple wells. Multiple triple wells are utilized and the word line switch transistors are grouped into triple wells based on word line voltage ranges used during the programming process. In one embodiment, for a given block, the word line switch transistors connected to data word lines are positioned in a first triple well and the word line switch transistors connected to selection and dummy word lines are positioned in a second triple well. This structure allows the triple wells to be biased differently.