The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 02, 2022
Filed:
Sep. 27, 2018
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Harishankar Sridharan, Santa Clara, CA (US);
Karthik Tyamgondlu, Chandler, AZ (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/26 (2006.01); G06F 1/28 (2006.01); G06F 1/00 (2006.01); G06F 11/30 (2006.01); H03K 3/00 (2006.01); G11C 7/10 (2006.01); H03K 17/687 (2006.01); H03K 19/00 (2006.01); H03K 19/0175 (2006.01); G11C 5/14 (2006.01); G11C 11/4096 (2006.01); H03K 19/0185 (2006.01); G11C 11/40 (2006.01); H03K 19/173 (2006.01); G11C 11/4074 (2006.01); G11C 11/4093 (2006.01); H03K 19/003 (2006.01); G11C 7/00 (2006.01); H03L 7/081 (2006.01);
U.S. Cl.
CPC ...
G11C 7/10 (2013.01); G06F 1/26 (2013.01); G06F 1/28 (2013.01); G11C 5/14 (2013.01); G11C 7/00 (2013.01); G11C 7/1057 (2013.01); G11C 7/1087 (2013.01); G11C 11/40 (2013.01); G11C 11/4074 (2013.01); G11C 11/4093 (2013.01); G11C 11/4096 (2013.01); H03K 17/687 (2013.01); H03K 17/6872 (2013.01); H03K 19/00 (2013.01); H03K 19/0005 (2013.01); H03K 19/0008 (2013.01); H03K 19/0013 (2013.01); H03K 19/00361 (2013.01); H03K 19/00384 (2013.01); H03K 19/0175 (2013.01); H03K 19/0185 (2013.01); H03K 19/017509 (2013.01); H03K 19/017518 (2013.01); H03K 19/017545 (2013.01); H03K 19/018521 (2013.01); H03K 19/018585 (2013.01); H03K 19/173 (2013.01); H03K 19/1733 (2013.01); H03L 7/0812 (2013.01);
Abstract
An apparatus is provided, where the apparatus includes a first transistor coupled between a supply node and an output node; a resistor and a second transistor coupled in series between the output node and a ground terminal; a circuitry to receive data, and to output a first control signal and a second control signal to respectively control the first transistor and the second transistor, wherein an output signal at the output node is indicative of the data, and wherein the first transistor is a N-type transistor.