The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 02, 2022

Filed:

May. 11, 2018
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Robert Nasry Hasbun, San Jose, CA (US);

Timothy M. Hollis, Meridian, ID (US);

Jeffrey P. Wright, Boise, ID (US);

Dean D. Gans, Nampa, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/42 (2006.01); G06F 13/16 (2006.01); G06F 13/40 (2006.01); G11C 5/06 (2006.01); G11C 5/02 (2006.01); G11C 11/4093 (2006.01); G11C 7/10 (2006.01); G11C 11/4096 (2006.01); G11C 5/04 (2006.01);
U.S. Cl.
CPC ...
G06F 13/1689 (2013.01); G06F 13/4068 (2013.01); G06F 13/42 (2013.01); G06F 13/4234 (2013.01); G11C 5/02 (2013.01); G11C 5/04 (2013.01); G11C 5/06 (2013.01); G11C 5/063 (2013.01); G11C 7/1012 (2013.01); G11C 7/1069 (2013.01); G11C 11/4093 (2013.01); G11C 11/4096 (2013.01);
Abstract

Methods, systems, and devices for communicating data with stacked memory dies are described. A first semiconductor die may communicate with an external computing device using a binary-symbol signal including two signal levels representing one bit of data. Semiconductor dies may be stacked on one another and include internal interconnects (e.g., through-silicon vias) to relay an internal signal generated based on the binary-symbol signal. The internal signal may be a multi-symbol signal modulated using a modulation scheme that includes three or more levels to represent more than one bit of data. The multi-level symbol signal may simplify the internal interconnects. A second semiconductor die may be configured to receive and re-transmit the multi-level symbol signal to semiconductor dies positioned above the second semiconductor die.


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